Department of Electronics (2016 - Present)
Electronics
ECE, Tarbiat Modares, Tehran, Iran
Amir Nikpaik received the B.S. degree in electrical engineering from Shahid Beheshti University, Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees in microelectronics from Tarbiat Modares University, Tehran, in 2010 and 2015, respectively. From 2014 to 2015, he was a Visiting Scholar with the System-on-Chip Laboratory, University of British Columbia, Vancouver, BC, Canada, where he focused on RF, mm-wave, and sub-mm-wave oscillators. He is currently an Assistant Professor of electrical and computer engineering with the Faculty of Electrical and Computer Engineering, Tarbiat Modares University, Tehran, Iran. His current research interests include noise analysis in high frequency and nonlinear circuits, frequency synthesizers, and mm-wave and terahertz circuit design for imaging applications. Dr. Nikpaik was a co-recipient of the Best Student Paper Award of the IEEE 2015 Radio-Frequency Integrated Circuit Symposium, Phoenix, USA.
Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This paper shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators in 65-nm CMOS. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. An architecture is proposed in which: 1) the core voltage-controlled oscillator is optimized to efficiently g
Achieving high output power in (sub-)THz voltage-controlled oscillators (VCOs) has been a severe design challenge in CMOS technology. In this work, an architecture for coupled terahertz (THz) VCOs is presented. The architecture utilizes four coupled triple-push VCOs and combines the generated third harmonic currents using slow-wave coplanar waveguide (S-CPW) at 300 GHz. Coupling four cores increases output power, and use of S-CPW reduces the loss and increases the quality factor of the VCO tank. It is shown that using S-CPW results in ~2.6 dB of lower loss as compared to the conventional CPW or grounded-CPW (GCPW) structures. The VCO is tuned using parasitic tuning technique and achieves 1.7% frequency tuning range (FTR). The proposed struc
Frequency synthesis at mm-wave range suffers from a severe tradeoff between phase noise (PN) and frequency tuning range (FTR). This work presents the analysis and compares the performance of fundamental-mode voltage-controlled oscillators (F-VCOs) to harmonic-mode VCOs (H-VCOs). It is shown that unlike a mm-wave F-VCO, an H-VCO can simultaneously achieve higher FTR and lower PN. An H-VCO architecture, denoted as self-mixing VCO (SMV), is presented where the VCO core generates both the first (fο) and second harmonic (2fο) and then mixes them together to obtain the desired mm-wave third-harmonic (3fο). Use of a Class-C push-push topology as the VCO core enhances the second-harmonic content to improve mixing efficiency, decreases parasitic
An analysis of the flicker noise conversion to close‐in phase noise in complementary metal‐oxide semiconductor (CMOS) differential inductance‐capacitance (LC)‐voltage controlled oscillator is presented. The contribution of different mechanisms responsible for flicker noise to phase noise conversion is investigated from a theoretical point of view. Impulse sensitivity function theory is exploited to quantify flicker noise to phase noise conversion process from both tail and core transistors. The impact of different parasitic capacitances inside the active core on flicker noise to phase noise conversion is investigated. Also, it is shown how different flicker noise models for core metal‐oxide semiconductor (MOS) transistors may res
There exists a fundamental limit in improving the phase noise performance of LC-tank oscillators. Impediments to reach this limit are first discussed, and then a clipping LC VCO topology based on dual tank is presented to mitigate them. This topology can approach within 3 dB of the maximum thermodynamically achievable figure-of-merit (FoM) limit. Compared to conventional class-B/C/D/F oscillators, it is capable of reducing both close-in and far-out phase noise. As a proof of concept, a prototype 4.17-4.95 GHz VCO in a 0.13-μm CMOS process achieves a phase noise of -97 and -143 dBc/Hz at 30 kHz and 3 MHz offset, respectively.
Achieving high tuning-range and low phase-noise simultaneously in mm-wave voltage-controlled oscillators (VCO) has been a severe design challenge. Our architecture, referred herein as a self-mixing VCO (SMV), utilizes a Class-C push-push VCO topology to generate the first (f 0 ) and second harmonics (2f 0 ) and then mixes them together to obtain the desired third harmonic (3f 0 ) component. Compared to a fundamental-mode VCO operating at 3f 0 in mm-wave band, the SMV architecture achieves superior frequency tuning range (FTR) and phase-noise (PN) performance. A Class-C topology enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance and reduces phase noise. A 52.8-to-62.5 GHz SMV prototype is desig
This paper describes a design procedure for mm-wave voltage controlled oscillator (VCO), based on large signal behavior of oscillator transconductance. Then, a new structure of LC-VCO is presented, which utilizes a transformer feedback to enhance the transconductance of the core transistors and to cancel the undesired parasitic effects. Using a 0.18-?m RF CMOS technology, the advantage of this VCO is examined by large signal analysis and simulation. The results illustrate improvement of 5dB in phase-noise and 70% in tuning-range, compared to enhanced active gain conventional transformer feedback VCO. Finally, a compact layout for transformer design is proposed.
This paper presents a new low phase noise quadrature voltage-controlled oscillator (QVCO). Coupling phase shifts of 90 in conjunction with center-tapped capacitor impedance transformers are exploited to optimally couple two VCOs. DC and AC path of the switching and coupling pairs are de-coupled to allow operation in saturation for large oscillation amplitudes. The switching and coupling transistor pairs operate in class-C mode which increases the DC to RF efficiency. Also, these transistors alternate from strong inversion to accumulation region, decreasing the intrinsic device flicker noise. Simulations confirm the superiority of the proposed circuit in comparison with the prior published QVCOs in terms of phase noise performance.
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