access deny [1301]
Research field:
Expert:
Phone:
Address:
Research field:
Expert:
Phone:
Address:
access deny [1026]
This paper presents a Class-E Power Amplifier (PA) design procedure for operation at mm-Wave frequencies, which accounts for the loss of passive components, ON-resistance (Ron) of the transistor, and its breakdown voltage (VBr). The quality factor of inductors is modeled with equivalent resistors and integrated into time-domain equations for the first time. The proposed procedure is examined for the design of a 24GHz Class-E PA in 130nm CMOS technology and compared with former best-known design recipes in the same technology node. Besides, a simplified design technique is introduced based on Ron-Cout (Cout is the transistor output capacitance) curves of the transistor versus its width, obtained by Harmonic Balance (HB) simulation. By the pr
This paper introduces a low power flip-flop based on the discrete-time parametric amplifier, with improved rise (fall) time, setup-time, hold-time, and area. Post-layout simulation result of the proposed flip-flop in a 180?nm CMOS technology with 3.33?GHz frequency illustrates about 21% of the power consumed by CML flip-flop and about 30% improvement in the clock-to-q delay. Also, the simulation shows improved rise (fall) time, lower data-to-q delay compared to dynamic CML and Footless flip-flop, lower area than Charge Steering flip-flops without the need for additional return-to-zero to non-return-to-zero conversion circuitry. When using this flip-flop as a slicer in a decision feedback equalizer (DFE) circuit of a serial link receiver of
This paper presents a new method to analyze nonidealities of N‐path circuits. This method utilizes Fourier transform of the impulse response of an N‐path circuit in the time domain to calculate the transfer functions. The time domain analysis makes the method simple and intuitive. Instead of conventional sophisticated calculations, this method limits the analysis to some integral calculations. This analysis can take into account two common nonidealities: parallel capacitance and overlapping clocks. The accuracy of the analysis is verified by simulations for both cases. Further, the analysis has been expanded to differential filters.
This paper presents a new high-speed low-power charge-steering latch, using a boosting technique for the tail capacitor, which is charged reversely in the reset phase. This technique decreases the source node voltage of the differential pair, which improves the output voltage swing. Analysis and post-layout simulation results of the proposed boosted charge-steering latch (BCS), in 65?nm CMOS technology, illustrate that for the same output swing and with about 28% tail capacitor of the conventional charge-steering latch, the maximum operating frequency is increased by about 12%. In the case of the same tail capacitor, the BCS latch gives the output swing of about 30% higher than that of conventional one for the low to moderate input swing, w
This paper presents the design and analysis of a millimeter-wave LNA-mixer, which adopts a low-noise single-to-differential conversion balun with low phase (gain) imbalance, using a common-source and a common-gate stage. Each stage employs a cascode transistor with inductors in the gate and source for improving noise, gain, and bandwidth performance. A new transformer-based network is proposed for broadband input matching. Also, a transformer network couples between transconductance and switching stage for independent biasing of two stages, which provides passive gain without extra power consumption and further noise reduction. To optimize the size of transistors and their current density, a new figure of merit is utilized which concurrent
In this paper a Surface Acoustic Wave (SAW) device with the wavelength of is proposed. Inter Digital Transducers (IDTs) of the device are fabricated through the photolithography method. (BA) 2 PbI 4 , a quasi 2D Ruddlesden Popper Perovskite (RPP), is used as piezoelectric material on the top of IDTs. The RF measurements of the SAW device are investigated and the resonance frequencies at 71.43 MHz and 289.83 MHz show the accurate matching of transmission (S21) and reflection (S11) spectrums.
Microwave holography technique reconstructs a target image using recorded amplitudes and phases of the signals reflected from the target with Fast Fourier Transform (FFT)-based algorithms. The reconstruction algorithms have two or more steps of two- and three-dimensional Fourier transforms, which have a high computational load. In this paper, by neglecting the impact of target depth on image reconstruction, an efficient Fresnel-based algorithm is proposed, involving only one-step FFT for both single- and multi-frequency microwave imaging. Numerous tests have been performed to show the effectiveness of the proposed algorithm including planar and non-planar targets, using the raw data gathered by means of a scanner operating in X-band. Finall
This paper presents a linear class-AB amplifier for envelope tracking of polar modulation. In this amplifier, by maintaining the phase margin, the capacitor size of the compensator is reduced, while a high gain-bandwidth is obtained. Hybrid Supply Envelope Modulator (HSEM) requires high gain-bandwidth, high slew-rate and low output impedance. In this work, due to low output impedance, the HSEM architecture is capable of reducing the switching noise up to 76MHz. Furthermore, owning to high slew-rate and high gain-bandwidth, the HSEM can quickly track the envelope of signal. Simulation of the proposed amplifier in 180 nm CMOS technology illustrates 55dB DC gain, 890 MHz gain-bandwidth, 1492 / 1518 slew-rate, and maximum output impedance of
This paper presents a low power lumped-element 3-dB coupler operating at different frequencies for application in multi-standard systems. The coupler is designed based on a method in which the return loss and isolation can be improved by adjusting the components quality factors. To this end, we use a tunable inductor, capable of generating adjustable inductor and negative resistance, in the coupler topology. By tuning the inductance and its quality factor independently, we achieve a hybrid coupler with low return loss and high isolation operating at different center frequencies. Moreover, the negative resistance, generated by the tunable inductor, compensates circuit losses that results in substantial improvement in the coupler insertion lo
In this study, Network Simulation Method (NSM) is applied to solve a onedimensional solute transfer problem governed by Transient Storage (TS) model in a mountain stream including dead zones. In this computational method, for each node of the discretized domain, the terms of governing equation are substituted by the equivalent electrical devices which are connected to each other based on Kirchhoff’s current law. Finally, the total electric circuit is solved using an appropriate electrical code to obtain the unknown value at the nodes. Because no analytical solutions for this model have been presented so far, to verify NSM, the problem is solved by Finite Volume Method (FVM), as well. According to the results, es
Introduction: Human activities everyday release a huge amount of domestic, industrial and agricultural waste into water bodies and continuously change the ecosystem conditions in the world. Considering the harmful effects of these pollutants entering water resources, study about pollution transfer in streams and predicting the pollutant concentration at downstream points seem to be important. For this purpose, the well-known classical advection-dispersion equation (ADE) was presented as the first attempt for describing mass transfer and energy transfer in physical systems. This equation is useful for channels with relatively prismatic and uniform cross-sections.Experimental studies carried out in rivers show that ADE is no longer applicable
This paper presents a 7-bit 15?× interleaved SAR ADC that operates up to 3?GS/s, using 180?nm CMOS technology. The ADC utilizes the transient information of a dynamic SAR voltage-comparator to resolve 2?bits per clock cycle, using a time-comparator block. Thus, only 5 clock cycles are needed to resolve 7?bits. This results in speed improvement of about 60%, compared to conventional ADC. Also, an improved Quasi C-2?C DAC structure with reduced internal node swing and reduced switching activity are utilized, which decreases the power consumption of DAC up to 65%. We employ the above techniques in designing a 7-bit SAR ADC, in which 3?bits are resolved with time-comparator blocks and 4?bits are resolved with a voltage-comparator. To calibrat
This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I‐V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter‐wave injection‐locked frequency dividers. To compensate the degradation of mixer transconductance (conversion‐gain) due to the degeneration effect, a neutralization technique is employed. Analyses are given for locking‐range and induced phase‐noise of the proposed divider for arbitrary injection strength. It is shown that the locking‐range, as a function of injection strength, is improved by increasing the fundamental component of transconductance. Using 180‐nm CMO
This paper presents an N-path filter with high out-of-band rejection using feed-forward technique. The structure utilizes two 4-path filters, one as the main-path and the other as auxiliary-path, and two TIAs to increase the order of the filter from two to four. As a result of this, and due to using two series resistors in the main-path, the out-of-band rejection is significantly improved. Analysis and simulations show that the series resistors can be chosen such that the NF degradation is below 2dB while the out-of-band rejection is improved by about 20 dB. Therefore, the trade-off between the insertion-loss and out-of-band rejection is relaxed compared to conventional N-path filter. Also, it is shown that decreasing the size of baseband c
Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This paper shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators in 65-nm CMOS. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. An architecture is proposed in which: 1) the core voltage-controlled oscillator is optimized to efficiently g
This paper presents a new circuit topology of millimetre-wave quadrature voltage-controlled oscillator (QVCO) using an improved Colpitts oscillator without tail bias. By employing an extra capacitance between the drain and source terminations of the transistors and optimising circuit values, a low-power and low-phase-noise (PN) oscillator is designed. For generating the output signals with 90? phase difference, a self-injection coupling network between two identical cores is used. The proposed QVCO dissipates no extra dc power for coupling, since there is no dc-path to ground for the coupled transistors and no extra noise is added to circuit. The best figure-of-merit is −188.5, the power consumption is 14.98–15.45?mW, in a standard 180-
Stability of low voltage regulated cascode (RGC) transimpedance amplifier (TIA) with level shifter path is analyzed and criterions for a well-behaved time response are derived. It is shown that there is a trade-off between the amplifier bandwidth and stability in this topology. Improving bandwidth by increasing transconductance of transistors leads to ringing in the step response of the amplifier and finally its instability. To add a degree of freedom to design of the low-voltage RGC circuit for high-speed optical receivers, a compensation technique is proposed in this paper and employed in a TIA circuit, designed in a 0.18 μm CMOS technology. Post layout simulation results show a gain of 52 dBΩ and bandwidth of 3 GHz in presence of a 2 p
A method to provide a low power tunable inductor is presented in which the inductance and its equivalent series resistance can be independently tuned. This equivalent series resistance can be also set to negative or zero value that is corresponding to inductor with ideal quality factor. In this method, a varactor is placed in parallel with a passive inductor and then, an active capacitor is placed in series with them. To this end, a low power Tunable Active Capacitor (TAC) is proposed which is capable of generating tunable capacitor and large negative resistance to compensate the loss of tunable inductor circuit. Also, the power consumption is low because of using a diode-connected transistor. A prototype of the proposed circuit is designed
In this paper, a Low Noise Variable Gain Amplifier in Ka-frequency band is designed. This amplifier is digitally controlled by using switching transistors which change the gain with an accuracy of 5-bit resolution (32 steps). The output phase shift should be minimized within a Dynamic Range of 15 dB. The proposed structure includes a Low Noise Amplifier and a Variable Gain Amplifier, with common-source structure and degenerative inductor. In the proposed structure, the main gain is achieved by LNA and the switching control bits are used in two stages of the VGA. Simulation illustrates a Noise Figure of 5. 6 dB; bandwidth of 5. 34 GHz; S11, S22 less than-14 dB and Dynamic Range of 15 dB. By using a “compensating inductor” in the source o